The length of the cipher key used is represented by Nk, where Nk is the number of 32-bit words in the cipher key. The AES standard, as currently defined, allows use of cipher keys with lengths of 128 bits (wherein Nk=4), 192 bits (Nk=6), or 256 bits (Nk=8). A particular implementation of the AES standard must support at least one of the standard cipher key lengths.

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Round constant generation block 402 comprises 9-bit round constant register 431 and 9-bit XOR adder 430. Round constant register 431 is seeded with the value ‘001101100’ at the start of the decryption of every block, which depends on decrypt-start signal 102b.


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This is followed by Nr−1 identical rounds of transformation, which include the above four inverse transformations, and wherein the AddRoundKey( ) transformation steps backwards through the key schedule. The final round (round Nr) does not include the InvMixColumns( ) transformation.

In an alternative embodiment, decryption unit 101 is configured to decrypt ciphertext encrypted using other variations of the Rijndael algorithm. Thus, decryption unit 101 can be modified to handle data block sizes of 192 bits or 256 bits. This would require modifications, known to one of ordinary skill in the art, to decryption block 102 to allow it to handle the different data block sizes, such as increasing the sizes of registers 201 and 203, expanding multiplexer 204, expanding mux block 202, and modifying the logic and counters of decryption controller 210. Decryption key generation block 103 can remain substantially unchanged for 128-bit cipher keys, and modified as described above for 192-bit and 256-bit cipher keys, with appropriate counter modifications, as necessary. In an alternative embodiment, decryption unit 101 can be modified to handle any cipher key size that is a multiple of 32 bits and any data block size that is a multiple of 32 bits by modifications similar to those described above for handling data block sizes other than 128 bits and cipher key sizes other than 128 bits.


In the preferred embodiment, control signals based on 2-bit column counter 214 are used as control signals by components of decryption key generation block 103 since they operate in four-count cycles. In alternative embodiments with different data block and/or cipher key sizes, components of decryption key generation block 103 may require control signals based on cyclical counters other than the column counter for proper operation.

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Unlike the 32-bit round constants provided and suggested by the AES standard, key generation block 103 uses 8-bit round constants, which are generated by round constant generation block 402 as described below. S-box 424 performs the SubBytes( ) operation on 8-bit signal 423a, which is the output of multiplexer 423.

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Decryption unit 101 comprises decryption block 102 and decryption key generation block 103

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In one embodiment, the invention is an apparatus for generating round-key words in accordance with a Rijndael algorithm. The apparatus comprises: (a) a key expansion register block, (b) a round constant generator, (c) a first XOR adder, (d) a transformation block, and (e) a second XOR adder. The key expansion register block comprises a key expansion register adapted to receive a final cipher key of a key expansion schedule in accordance with the Rijndael algorithm, and the key expansion register block is adapted to shift the contents of the key expansion register. The round constant generator is adapted to generate a current round constant based on a seed value and in response to a first control signal.


A preferred embodiment of the present invention has been described. Numerous variations and equivalent implementations, which would be known to a person of ordinary skill in the art of digital circuit design, are possible without departing from the teachings of the present invention. For example, the numbering of bits, bytes, and/or words and their designations as least significant or most significant is reversible without affecting the operation of the described embodiment, or of other embodiments of the present invention. For another example, decryption register 203 can burst out its data through wider or narrower output paths, that would then require correspondingly fewer or more clock cycles to burst out.

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Current approaches for implementing the AES-Rijndael algorithm in semiconductor devices typically use Nk·(Nr+1) registers to store the entire key expansion table on chip. This storage requires an undesirably large number of gates and consequent large chip area.

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The initial stage of the decryption is performed by bypassing InvSubBytes( ) and InvMixColumns( ) operations, and performing the AddRoundKey( ) operation, which is followed by the InvShiftRows( ) transformation for round one of the decryption. Then, in rounds one through nine, the data in decryption register 203 undergoes nine rounds of transformations by the four inverse transformations of decryption.


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In-bit counter 211 counts the bits coming into shift register 201, incrementing with every cycle of DSR_CLK, and is used to determine when 128 data bits have shifted in, which in turn triggers 128th-bit control signal 210a, which in turn triggers decryption-busy control signal 210f and decrypt-start control signal 102b. There may be a slight lag in the triggering of decryption-busy control signal 210f and decrypt-start control signal 102b due to the operation of an optional synchronizer.


Key generation block 103 provides key word signal 103b to XOR adder 207 in decryption block 102 of FIG

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Decryption key generation block 103 generates one key word for decryption block 102 on every cycle of state machine clock SM_CLK, following the initial population of expansion register 411. Thus, 45 cycles would be needed for on-the-fly round key generation using a 128-bit cipher key, 53 cycles using a 192-bit cipher key, and 61 cycles using a 256-bit cipher key. Alternative implementations may require additional clock cycles.

Temporary register 422 comprises four bytes and polls its four source multiplexers on the falling edge of every cycle of state machine clock SM_CLK. Multiplexer 425 provides its output to bit locations [7:0] of temporary register 422, mux 426 to locations [15:8], mux 427 to locations [23:16], and mux 428 to locations [31:24].


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In an alternative embodiment, decryption block 102 is arranged to use the equivalent inverse cipher algorithm of the AES standard, with requisite modifications to decryption block 102, as are known to one of ordinary skill in the art. Such modifications would include re-arrangements of the components of decryption block 102, and applying the InvMixColumns( ) transformation in rounds 1 through Nr−1 to the key words received from key generation block 103 via signal 103b. In a further alternative embodiment, decryption block 102 is arranged using another equivalent inverse cipher algorithm, with requisite modifications to decryption block 102, as are known to one of ordinary skill in the art. Such modifications would include re-arrangements of the components of decryption block 102, and application of any necessary transformation in rounds 1 through Nr−1 to the key words received from key generation block 103 via signal 103b.

Key expansion register block 401 receives, shifts and stores within key expansion register 411 the words of the round keys, and further comprises and multiplexers 407, 408, 409, 410, and 412. The four 32-bit multiplexers 407, 408, 409, and 410 provide their outputs to the four 32-bit sections, designated w, w, w, and w, respectively, of 128-bit key expansion register 411, which polls the above four multiplexers on the rising edge of every cycle of state machine clock SM_CLK. If decrypt-start signal 102b, which is a control signal for 32-bit multiplexers 407, 408, 409, and 410, is high, then these four multiplexers output 32-bit words w_eks, w_eks, w_eks, and w_eks, respectively, of key shadow register 406.

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